1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and in particular to an improved method for fabricating a semiconductor memory device which can form a storage electrode contact and a contact plug according to a self aligned method.
2. Description of the Background Art
The high integration of a semiconductor memory device such as a DRAM and an SRAM is accompanied with a decrease of a cell area. Therefore, an occupied width of a capacitor on a substrate must be reduced. It is important to reduce the occupied width of the capacitor in fabricating a high capacity memory device. The occupied width of the capacitor must be reduced in consideration of stabilized capacitance.
As publicly known, the capacitance of the capacitor is proportional to a surface area of an electrode and a dielectric constant of a dielectric material, and inversely proportional to an interval between the electrodes, namely a thickness of the dielectric material. At this time, a method for decreasing the thickness of the dielectric material has a limit due to leakage current. Accordingly, the stabilized capacitance is obtained by increasing the surface area of the electrode. For example, a storage electrode having a three-dimensional structure such as a cylinder, a pin and a stack type obtains the stabilized capacitance of the capacitor by increasing its surface area.
FIG. 1 is a plan view illustrating masks used to form a memory cell of the semiconductor memory device. Reference numeral 102 denotes an active mask, 104 denotes a gate electrode mask, 106 denotes a contact plug mask, 108 denotes a bit line contact mask, 110 denotes a bit line mask, and 112 denotes a storage electrode contact mask.
A conventional method for fabricating a semiconductor memory device by using the aforementioned masks will now be described with reference to FIGS. 2A to 2D. Here, Figures at the left side are cross-sectional diagrams taken along line a-axe2x80x2 in FIG. 1, and Figures at the right side are cross-sectional diagrams taken along line b-bxe2x80x2 in FIG. 1.
Referring to FIG. 2A, a device isolation film 202 is formed at a predetermined portion of a semiconductor substrate 200. A gate insulation film 204, a conductive film for a gate electrode and a first hard mask film 208 are sequentially formed on the semiconductor substrate 200. The first hard mask film 208 and the conductive film for the gate electrode are patterned according to an etching process using the gate electrode mask 104 as shown in FIG. 1, thereby forming a gate electrode 206. Source/drain regions 210, 212 are formed on the exposed semiconductor substrate 200 according to an impurity ion implantation process. A first etch barrier film 214 is formed over the resultant structure. A first interlayer insulation film 216 is evenly formed on the first etch barrier film 214.
The first interlayer insulation film 216 is etched by employing as an etch barrier the contact plug mask 106 as shown in FIG. 1 and the first etch barrier film 214, and then the first etch barrier film 214 is partially removed, thereby forming a contact hole exposing the source region 210 to be connected to a capacitor and the drain region 212 to be connected to a bit line. The contact hole is filled with a conductive film. Thereafter, the conductive film is etched back to expose the first interlayer insulation film 216, thereby forming first and second contact plugs 218a, 218b. 
Referring to FIG. 2B, a second interlayer insulation film 220 is formed on the semiconductor substrate 200 where the first and second contact plugs 218a,218b have been formed. The second interlayer insulation film 220 is etched to expose the second contact plug 218b on the drain region, by performing an etching process using the bit line contact mask 108 as shown in FIG. 1. A conductive film 222 for a bit line is formed on the second interlayer insulation film 220 to contact the exposed second contact plug 218b. A second hard mask film 224 is formed on the conductive film 222 for the bit line.
Referring to FIG. 2C, the second hard mask film 224, the conductive film 222 for the bit line and the second interlayer insulation film 220 are sequentially etched according to an etching process using the bit line mask 110 as shown in FIG. 1, thereby forming a bit line 222a and a contact hole exposing the first contact plug 218a on the source region 210 at the same time. A second etch barrier film 226 is formed over the resultant structure. A third interlayer insulation film 228 is evenly formed on the second etch barrier film 226. A third etch barrier film 230 is formed on the third interlayer insulation film 228.
Referring to FIG. 2D, a sacrificed oxide film 234 is formed on the third etch barrier film 230. The sacrificed oxide film 234, the third etch barrier film 230, the third interlayer insulation film 228 and the second etch barrier film 226 are etched according to an etching process using the storage electrode contact mask 112 as shown in FIG. 1, thereby forming a storage electrode contact exposing the first contact plug 218a on the source region 210. A conductive film 236 for a storage electrode is formed to fill up a part of the storage electrode contact.
Thereafter, the memory cell including the capacitor having a stacked structure of a storage electrode, dielectric film and plate electrode is formed according to generally-known succeeding processes.
However, in the conventional method for fabricating the semiconductor memory device, the storage electrode contact is self-aligned with the gate electrode and the bit line, but not with the second contact plug on the source region.
Therefore, when the etching process using the storage electrode contact mask as shown in FIG. 1 is carried out in order to form the storage electrode contact, a process defect may be generated due to the misalignment of the mask. In addition, the storage electrode and the contact plug do not completely contact each other, thereby reducing the capacitance of the capacitor.
Accordingly, an object of the present invention is to provide a method for fabricating a semiconductor memory device which can form a storage electrode contact and a contact plug in a self aligned method.
In order to achieve the above-described object of the present invention, a method for fabricating a semiconductor memory device includes the steps of: providing a semiconductor substrate where a transistor consisting of a gate electrode and source and drain regions has been formed, a first contact plug and a second contact plug being respectively formed on the source and drain regions; forming a bit line electrically connected to the second contact plug on the drain region, and simultaneously forming a contact hole exposing the first contact plug on the source region over the resultant structure; forming an etch barrier film having a uniform thickness at the inner walls of the contact hole and on the bit line; forming an interlayer insulation film on the etch barrier film; forming a storage electrode contact, by etching the interlayer insulation film and the etch barrier film on the first contact plug; forming a third contact plug electrically connected to the first contact plug in the storage electrode contact; and forming on the third contact plug a capacitor having a stacked structure of a storage electrode electrically connected to the third contact plug, and a dielectric film and a plate electrode surrounding the storage electrode.
There is also provided a method for fabricating a semiconductor memory device including the steps of: forming a gate electrode on a semiconductor substrate; forming source and drain regions on the semiconductor substrate at both sides of the gate electrode; forming a first etch barrier film having a uniform thickness over the resultant structure; forming a first interlayer insulation film on the first etch barrier film; forming a first contact hole exposing the source and drain regions, by etching the first interlayer insulation film and the first etch barrier film; forming a first contact plug on the source region and a second contact plug on the drain region, by filling up a conductive film in the first contact hole; forming a second interlayer insulation film exposing the second contact plug on the first and second contact plugs and the first interlayer insulation film; sequentially forming a conductive film for a bit line and a second hard mask film on the exposed second contact plug and the second interlayer insulation film; forming a bit line contacting the second contact plug and a second contact hole exposing the first contact plug, by patterning the second hard mask film and the conductive film for the bit line; forming a second etch barrier film at the inner walls of the contact hole and on the second hard mask film; forming a third interlayer insulation film on the second etch barrier film to completely fill up the second contact hole; forming on the third interlayer insulation film a third etch barrier film exposing the third interlayer insulation film region on the first contact plug; forming a third contact hole exposing the first contact plug, by etching the exposed third interlayer insulation film region and the second etch barrier film on the first contact plug; forming a third contact plug electrically connected to the first contact plug, by filling up a conductive film in the third contact hole; forming a sacrificed oxide film on the third etch barrier film and the third contact plug; forming a fourth contact hole exposing the third contact plug, by etching a predetermined portion of the sacrificed oxide film; and forming over the resultant structure a capacitor being electrically connected to the third contact plug, and having a stacked structure of a storage electrode, dielectric film and plate electrode.
In addition, there is provided a method for fabricating a semiconductor memory device including the steps of: forming a gate electrode on a semiconductor substrate; forming source and drain regions on the semiconductor substrate at both sides of the gate electrode; forming a first etch barrier film having a uniform thickness over the resultant structure; forming a first interlayer insulation film on the first etch barrier film; forming a first contact hole exposing the source and drain regions, by etching the first interlayer insulation film and the first etch barrier film; forming a first contact plug on the source region and a second contact plug on the drain region, by filling up a conductive film in the first contact hole; forming a second interlayer insulation film exposing the second contact plug on the first and second contact plugs and the first interlayer insulation film; sequentially forming a conductive film for a bit line and a second hard mask film on the exposed second contact plug and the second interlayer insulation film; forming a bit line contacting the second contact plug and a second contact hole exposing the first contact plug, by patterning the second hard mask film and the conductive film for the bit line; forming a second etch barrier fiilm at the inner walls of the contact hole and on the second hard mask film; forming a third interlayer insulation film on the second etch barrier film to completely fill up the second contact hole; forming on the third interlayer insulation film a third etch barrier film exposing the third interlayer insulation film region on the first contact plug; forming a sacrificed oxide film on the third etch barrier film; forming a storage electrode contact, by etching the sacrificed oxide film, the third interlayer insulation film and the second etch barrier film on the first contact plug; forming a third contact plug electrically connected to the first contact plug at the lower portion of the storage electrode contact, by forming a conductive film for a storage electrode at the inner walls of the storage electrode contact and on the sacrificed oxide film; forming a storage electrode, by removing the conductive film for the storage electrode on the sacrificed oxide film and the sacrificed oxide film; and sequentially forming a dielectric film and a plate electrode on the storage electrode in order to form a capacitor.